Today's Systems on a Chip (SoC) have very high level of analog integration with multiple voltage regulators, voltage monitors, analog to digital and digital to analog converters, power on reset controllers and other systems which significantly increase the scope and complexity of manufacturing test coverage as well as the cost of testing. In order to reduce the SoC test time without compromising the test coverage and quality, a large number of analog test pins are required to enable the parallel testing of a number of analog modules. The analog test pins are normally dedicated pins that not only increase the package cost, but also reduce the number of available digital test pins due to limited number of channels provided by the Automated Test Equipment (ATE). This, in turn leads to increased test time for the digital logic as well.